In recent years, with advances in process miniaturization, the number of failure modes that can occur in semiconductor memories, etc., has been increasing. There are some defectives that cannot be completely eliminated by a high-temperature burn-in test or the like alone.
If pattern-dependent defectives detectable only by a long-duration running test are to be detected, it will take a prohibitively long test time because of increased integration. There is therefore a need for effective test conditions that do not depend on operation patterns.
Patent document 1 cited below as a prior art document relevant to the present invention discloses a test apparatus equipped with a means for setting the rise and fall times of the supply voltage to be applied to a semiconductor integrated circuit to arbitrarily selected values, thereby making it possible to accurately detect manufacturing defects attributable to the rise and fall times of the supply voltage.
On the other hand, patent document 2 cited below discloses an accelerated life test method for a semiconductor integrated circuit in which the test is performed by applying a bias voltage to the semiconductor integrated circuit under heat and, between supply voltage and signal voltage, at least the supply voltage is periodically reset to a low level where a latch-up current is shut off.
Patent document 3 cited below discloses a stress application amount control method that controls the amount and timing of stress application to each circuit block as desired; more specifically, a power supply switch is provided for each circuit block, and the power supply switch is individually controlled during a burn-in test to adjust the power supply time, i.e., the amount of stress, for each individual circuit block, thereby making it possible to apply a necessary and sufficient amount of stress to the circuit block that requires the longest stress application time, while preventing application of excessive stress to the other circuit blocks.                Patent document 1: Japanese Unexamined Patent Publication No. H06-118128        Patent document 2: Japanese Unexamined Patent Publication No. H07-174816        Patent document 3: Japanese Unexamined Patent Publication No. 2004-226220        